Which Of The Following Is A Shift Register Counter

Shift Registers

W. Bolton , in Programmable Logic Controllers (Sixth Edition), 2015

Summary

The term register is used for an electronic device in which information tin be stored. The shift register is a number of internal relays grouped together that permit stored bits to be shifted from one relay to some other. With the shift register information technology is possible to shift stored bits. Shift registers require three inputs: one to load information into the commencement location of the annals, one as the command to shift data along past 1 location, and one to reset or clear the register of data. The grouping together of internal relays to form a shift register is washed automatically by a PLC when the shift annals role is selected.

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Spread spectrum signaling in wireless communications

S.L. Miller , in Academic Press Library in Mobile and Wireless Communications, 2016

10.one.vi Code Sequences

In SS systems, the code sequences that are used should follow a deterministic format so that they can exist identically reproduced at the transmitter and receiver, yet they should exhibit properties of randomness so that information technology is difficult for a potential eavesdropper to identify the sequence existence used. Additionally, in club to ease the process of code synchronization at the receiver, it is desirable that the sequence used is as dissimilar as possible from any time shifted version of itself. In other words, the auto-correlation part of the code sequence should be uniformly low for all possible nonzero offsets.

It is mutual in SS systems to use code sequences which are the output of a binary shift register (SR) with feedback. A generic northward-phase SR is shown in Fig. 10.ten.

Fig. 10.x. A binary linear feedback shift register.

The SR is described in terms of a set of feedback connections, h ₀, h ₁, …, h _{due north} , where h _i = one indicates the presence of a feedback connectedness at the ith position, and h _i = 0 indicates no connexion. It is common to describe the feedback connections in terms of a polynomial:

$h(\mathrm{10})=h_0+h_1\mathrm{ten}+h_2{x}^{\mathrm{two}}+\cdots +h_n{x}^n.$

The SR, when clocked, produces a periodic sequence of 0 and 1   s. Since there are n binary storage elements, there are a total of 2 ⁿ possible states in which the SR tin can be. Once it returns to its starting state it volition repeat the output sequence it has produced upwards to that point. The all-goose egg country needs to exist avoided since in one case the SR enters the all-zero state it will be stuck in that location and will produce an (undesirable) output sequence of all zeros. Therefore, at that place are a maximum of ii ^{due north} − one states the SR can cycle through and hence the SR produces a periodic output sequence whose period is no longer than ii ⁿ − 1 $.25. An SR which produces an output sequence which achieves this maximum menstruation is called a maximal length linear feedback shift register (MLLFSR) and the sequences they produce are called MLLFSR sequences. Since this acronym is longer than most people adopt, the shortened term thou-sequence ^ane is more ordinarily used.

Not every polynomial, h(x), will produce an m-sequence. Polynomials which practise produce an grand-sequence are known every bit primitive polynomials. Tables of primitive polynomials can be plant in many books on spread spectrum (eg, Peterson et al. [5]) or mistake correction coding (eg, Peterson and Weldon [fifteen]) and are often given in octal form. A brusque tabular array is provided in Table 10.2. Every bit an example of how to use that table, the n = 5 entry will provide a primitive polynomial which volition produce an one thousand-sequence of length 2⁵ − 1 = 31. The octal entry 45 converts to the binary number 100101 which defines the polynomial h(x) = 1 + 10 ^two + ten ⁵. The corresponding five-phase MLLFSR is shown in Fig. 10.11. Also, if h(x) is a polynomial of caste n which produces an m-sequence of length N = 2 ^northward − 1, and so its reciprocal (defined as ten ^northward h(x ⁻¹)) also generates an m-sequence. Typically, tables of primitive polynomials practise not include both a polynomial and its reciprocal. And then at that place are actually six m-sequences of degree v (length 31) although the tabular array merely lists three.

Tabular array 10.two. Primitive Polynomials in Octal Form

Degree (northward)	Polynomial (Octal)
2	7
3	thirteen
4	23
5	45, 75, 67
6	103, 147, 155
7	211, 217, 235, 367, 277, 325, 203, 313, 345
8	435, 551, 747, 453, 545, 537, 703, 543

Fig. x.11. The five-phase MLLFSR specified by the octal number 45.

In the context of DS-SS, a binary code sequence is converted to a spreading waveform by start converting the bits from a {0, 1} format to a {+1, −1} format and and so modulating the sequence of bits with a fleck waveform. So if b is a sequence of bits with b _i ∈{0, 1}, then form the sequence c where $c_i={(-1)}^{b_i}.$ Finally, create the spreading waveform co-ordinate to

(10.i) $\begin{array}{l}\hfill c(t)=\sum _{\mathrm{thou}}{c}_{k}p(t-k{T}_c),\end{array}$

where p(t) is the chip pulse shape (ofttimes rectangular pulses are used but other options are possible). For a lawmaking sequence of period Due north, this will produce a spreading waveform which is periodic with a period of NT _c. In some applications, we may choose the period of the code sequence such that the spreading waveform repeats once every symbol interval (ie, N = T _{due south}/T _c). Such a lawmaking is referred to as a short code. Alternatively, it is likewise common to utilise codes that take a very long period then that the resulting spreading waveform does not repeat for many symbol intervals. Such codes are called long codes. Fundamentally, it is naught most the lawmaking that actually makes it long or brusque. Rather information technology is the ratio of the number of fries per chip in the SS system and how that relates to the period of the code sequence that distinguishes a short code from a long one.

In FH-SS, an North = 2 ^k -ary hopping blueprint could easily exist formed from a binary code sequence by grouping the code sequence into m-bit segments. Suppose, for example, our FH organization uses 64 hopping bins. Starting with a binary g-sequence of flow 255 and grouping the bits into six-bit words would produce a sequence of 64-ary numbers that appear random. Also, since half-dozen and 255 are relatively prime, the resulting 64-ary sequence would notwithstanding have a period of 255. Naturally, many other possibilities abound for mapping a binary code sequence into a nonbinary hopping pattern.

In the context of DS-CDMA where multiple dissimilar DS-SS signals must be created, information technology is necessary to use a set of code sequences that accept good cross-correlation properties. That is, each user should have a code sequence that is equally dissimilar as possible to every other code sequence in the prepare. In the case of synchronous CDMA where we practise not have to worry about the different users signals being offset in fourth dimension with respect to 1 some other, information technology is common to employ a gear up of orthogonal sequences, the near common of which are the so-called Walsh codes, which are taken as rows from a Hadamard matrix. These sequences can be generated through a simple recursion equally follows. Define the matrix, H ₀ = [1] and so create a sequence of matrices, H _n , n = one, ii, 3, … according to the recursion

${\mathit{H}}_{k+1}=\left[\begin{array}{c}\begin{array}{cc}{\mathit{H}}_{\mathrm{1000}}& {\mathit{H}}_{\mathrm{grand}}\\ {\mathit{H}}_k& -{\mathit{H}}_k\end{array}\end{array}\right].$

The resulting Hadamard matrix H _n will be a two ⁿ × ii ⁿ matrix whose elements are ± 1 valued and whose rows constitute an orthogonal gear up. That is, if c _k is the sequence corresponding to the yardthursday column of the matrix H _n , and then ${\mathit{c}}_m^T{\mathit{c}}_{\mathrm{1000}}=0$ for all one thousand≠m. The structure of a few brusque Walsh codes is shown in Fig. ten.12.

Fig. 10.12. Generation of an orthogonal set of Walsh codes.

In asynchronous DS-CDMA, we want each lawmaking sequence to be uncorrelated to not only every other code sequence in the set, but also to any time shift of any other code sequence in the set. Let c _k (t) be the spreading waveform assigned to user 1000. In order to keep the common interference to a minimum that each user'due south signal presents to another user'due south receiver, the spreading waveforms should be designed such that ${\int }_{T_{\mathrm{southward}}}{c}_k(t-{\tau }_k)c_m(t-{\tau }_m)dt\approx 0$ for any values of the time delays τ _k and τ _m and for any k≠grand. The menses of integration for the correlation integral is the symbol elapsing. For CDMA systems employing short codes, this corresponds to the period of the spreading waveforms, so we wish to keep the periodic cantankerous-correlation part of the spreading waveforms uniformly low. For a CDMA system with long codes, the catamenia of integration may be only a modest fraction of the catamenia of the spreading waveform, and therefore, the resulting correlation is only a partial correlation function.

For the case of short codes, in that location are a number of families of codes that take been designed to have skilful cross-correlation and auto-correlation properties. Many are synthetic from pairs of m-sequences that are known to have expert cross-correlation values. To describe such families of sequences, using the notation of Sarwate and Pursely [xvi], let b be an yard-sequence of length Northward, and let T be the correct circadian shift operator so that T b is equal to the sequence b cyclically shifted i identify to the correct. T ^m b would then cyclically shift b by m places to the right.

A ready of N + 2 sequences of length N can be formed from two m-sequences of length N, b ₁ and b _two, by amalgam the following set

$\mathit{Thou}=\left\{{\mathit{b}}_{\mathrm{ane}},{\mathit{b}}_{\mathrm{ii}},{\mathit{b}}_1\oplus {\mathit{b}}_{\mathrm{ii}},{\mathit{b}}_1\oplus T{\mathit{b}}_2,{\mathit{b}}_1\oplus T{\mathit{b}}_2^2,\dots ,{\mathit{b}}_{\mathrm{one}}\oplus T^{N-1}{\mathit{b}}_2\right\}.$

This prepare is known equally the set of Gold codes [17, 18] and has the property that if b ₁ and b ₂ have a pinnacle cross-correlation of r, so all pairs of codes in the Gilt set up volition also take a peak cross-correlation of r. Hence, if we tin can find one pair of 1000-sequences with proficient cross-correlation, and then we can construct a family of North + two sequences, all of which have equally expert cross-correlation.

Another common family of sequences is the then-chosen Kasami fix [19, 20]. In this case, we choose b _one to be an g-sequence of length N = two ⁿ − 1, where n is an even integer. Next, choose b ₂ to be an chiliad-sequence of length $2^{n/2}-1=\sqrt{N+\mathrm{one}}-\mathrm{one}$ . The Kasami set then consists of the set of $\sqrt{N+1}$ sequences:

$\mathit{K}=\left\{{\mathit{b}}_{\mathrm{one}},{\mathit{b}}_{\mathrm{one}}\oplus {\mathit{b}}_2,{\mathit{b}}_{\mathrm{ane}}\oplus T{\mathit{b}}_{\mathrm{two}},{\mathit{b}}_1\oplus T{\mathit{b}}_{\mathrm{two}}^{\mathrm{two}},\dots ,{\mathit{b}}_{\mathrm{ane}}\oplus T^{2^{\mathrm{north}/2}-2}{\mathit{b}}_2\right\}.$

The tiptop cross-correlation of this set will exist $\left(\sqrt{N+1}+1\right)/N$ . For example, if we choose North = 63, the Kasami set will provide a gear up of 8 sequences of length 63 with a peak cross-correlation of 9/63. By comparison, the Gilded gear up volition provide 65 sequences of length 63 whose peak cross-correlation is 17/63.

In closing, it should exist pointed out that there is a direct human relationship between families of sequences that are commonly considered for spreading codes and codewords that are found in certain low-rate cyclic cake codes [16]. It turns out that the set up of Gold codes are cipher more than than a subset of the codewords of a BCH code. For example, the length 63 Gold codes previously mentioned are found in the set up of codewords of a (63, 10) binary circadian BCH lawmaking. The point here is that if you lot want a prepare of sequences with good cross-correlation properties, you need non search any farther than a volume on error correction codes.

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Digital Edifice Blocks

Sarah L. Harris , David Harris , in Digital Design and Figurer Compages, 2022

5.4.2 Shift Registers

A shift register has a clock, a series input Southward _in, a serial output S _out, and N parallel outputs Q _North−1:0, as shown in Effigy 5.35. On each rising edge of the clock, a new bit is shifted in from S _in and all the subsequent contents are shifted forward. The final fleck in the shift annals is bachelor at Southward _out. Shift registers tin can be viewed equally series-to-parallel converters. The input is provided serially (one bit at a time) at S _in. After Northward cycles, the past Due north inputs are available in parallel at Q.

Effigy v.35. Shift register symbol

A shift register can be constructed from Northward flip-flops continued in series, equally shown in Effigy v.36. Some shift registers also accept a reset bespeak to initialize all of the flip-flops.

Figure 5.36. Shift annals schematic

A related excursion is a parallel-to-serial converter that loads N bits in parallel, and so shifts them out 1 at a time. A shift annals can be modified to perform both series-to-parallel and parallel-to-serial operations by adding a parallel input D _N−1:0 and a command signal Load, as shown in Figure 5.37. When Load is asserted, the flip-flops are loaded in parallel from the D inputs. Otherwise, the shift register shifts normally. HDL Example v.five describes such a shift annals, and Figure 5.38 shows the resulting hardware.

Effigy 5.37. Shift annals with parallel load

HDL Example v.five

Shift Register With Parallel Load

SystemVerilog

module shiftreg #(parameter North = 8)

  (input   logic   clk,

  input   logic   reset, load,

  input   logic   sin,

  input   logic [Due north–1:0] d,

  output logic [N–1:0] q,

  output logic   sout);

  always_ff @(posedge clk, posedge reset)

  if (reset)   q <= 0;

  else if (load)   q <= d;

  else   q <= {q[N–2:0], sin};

  assign sout = q[N–1];

endmodule

VHDL

library IEEE; utilise IEEE.STD_LOGIC_1164.ALL;

entity shiftreg is

  generic(N: integer := 8);

  port(clk, reset: in   STD_LOGIC;

  load, sin:   in   STD_LOGIC;

  d:   in   STD_LOGIC_VECTOR(N–1 downto 0);

  q:   out STD_LOGIC_VECTOR(N–ane downto 0);

  sout:   out STD_LOGIC);

finish;

architecture synth of shiftreg is

begin

  process(clk, reset) brainstorm

  if reset = '1' then q <= (OTHERS => '0');

  elsif rising_edge(clk) and so

  if load then   q <= d;

  else   q <= q(N–2 downto 0) & sin;

  terminate if;

  end if;

  end process;

  sout <= q(N–ane);

stop;

Effigy 5.38. Synthesized shiftreg

Browse Chains*

Shift registers are frequently used to test sequential circuits, using a technique called browse chains. Testing combinational circuits is relatively straightforward. Known inputs chosen test vectors are applied, and the outputs are checked against the expected outcome. Testing sequential circuits is more hard because the circuits have country. Starting from a known initial status, a large number of cycles of test vectors may be needed to put the circuit into a desired state. For example, testing that the most meaning chip of a 32-bit counter advances from 0 to 1 requires resetting the counter, then applying 2³¹ (near two billion) clock pulses!

Don't confuse shift registers with the shifters from Section 5.2.v. Shift registers are sequential logic blocks that shift in a new flake on each clock edge. Shifters are unclocked combinational logic blocks that shift an input by a specified amount.

To solve this trouble, designers like to be able to directly observe and control all of the machine'south country. This is done by calculation a test mode in which the contents of all flip-flops can be read out or loaded with desired values. Most systems have too many flip-flops to dedicate individual pins to read and write each flip-flop. Instead, all flip-flops in the system are continued together into a shift annals called a scan chain. In normal performance, the flip-flops load data from their D input and ignore the scan concatenation. In test mode, the flip-flops serially shift their contents out and shift in new contents using S _in and South _out. The load multiplexer is usually integrated into the flip-flop to produce a scannable flip-bomb. Figure v.39 shows the schematic and symbol for a scannable flip-flop and illustrates how the flops are cascaded to build an N-bit scannable register.

Figure 5.39. Scannable flip-flop: (a) schematic, (b) symbol, and (c) N-fleck scannable annals

For instance, the 32-chip counter could be tested by shifting in the pattern 011111…111 in test mode, counting for 1 bike in normal fashion, then shifting out the upshot, which should be 100000…000. This requires only 32 + 1 + 32 = 65 cycles.

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Counters and registers

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. Forest MA, DPhil , in Digital Logic Blueprint (Quaternary Edition), 2002

seven.15 Shift registers

A shift register is a sequential logic device which consists of a cascade of FFs contained in a single IC parcel. The output of each FF in the cascade is connected to the input of the succeeding FF, and information can be shifted from left to right or vice versa by the clock which is oftentimes referred to as the shift pulse. A basic four-stage register is shown in Figure 7.23 along with a series of timing diagrams. The register consists of 4 abaft edge triggered master/slave JKFFs which, alternatively, could be either primary/slave SR or D flip-flops. The timing diagrams illustrate the serial movement of 1 bit of data from the input of the register to its output. This functioning requires four clock pulses, the data moving from 1 FF in the cascade to the succeeding one on the receipt of the side by side clock pulse.

Figure seven.23. Basic iv-bit shift register with timing diagrams

Shift registers can exist classified into four distinct groups.

ane.

Series-in/serial-out (SISO), in which information can be moved serially in and out of the annals, ane bit at a fourth dimension.

ii.

Series-in/parallel-out (SIPO), in which the register is loaded serially, i bit at a time, and when an output is required the data stored in the annals can be read in parallel course.

3.

Parallel-in/serial-out (PISO), in which all the flip-flops are loaded simultaneously and when an output is required, the data stored is removed serially from the annals one bit at a time nether clock control.

four.

Parallel-in/parallel-out (PIPO), in which all the flip-flops in the register are loaded simultaneously, and when an output is required the flip-flops are read simultaneously.

Additional to the input and output terminals, a shift register will take an asynchronous clear concluding which is used to drive all the FFs in the register to logic 0. For those shift registers having parallel data inputs, an asynchronous preset or load is required for entering the data pattern into the register. A clock input is also required for shifting data through the register.

It is besides possible to classify shift registers co-ordinate to their input arrangements:

1.

Double-rails input. For this blazon of register there are two input terminals for either the J and K inputs or, alternatively, the S and R inputs.

2.

Single-rail input, as illustrated in Figure seven.23. Hither the beginning flip-flop in the cascade has been converted into a DFF by placing an inverter between the J and K input lines.

There can also exist double-rail output, where the true and complementary outputs of the terminal flip-flop in the register are brought out to separate pins, or, alternatively, there can exist a single-rail output where only the true output of the last flip-flop is fabricated available at a pin.

Data can be transferred by shift registers in either serial or parallel class. Series transfer between two 4-bit registers will require four clock pulses and one interconnection, while parallel transfer between two registers needs four interconnections. The type of transfer to be used depends upon the distance between the sending and receiving registers. For registers which are well-nigh to one some other, parallel transfer volition exist faster, fifty-fifty if more interconnections are needed, but for registers some altitude apart, the large number of interconnections required would prove to be uneconomic both in terms of cost and space.

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Electronic Circuits: Digital

Louis E. FrenzelJr., in Electronics Explained (2d Edition), 2018

Shift Registers

A shift register (SR) is similar a storage annals, but the bits stored at that place may exist shifted from one FF to the next every bit each clock pulse occurs. Fig. 5.17A shows how serial binary data is shifted into the SR for storage. As new information is shifted in, the existing data will be shifted out and sent to another excursion. Fig. v.17B shows data being shifted out as binary 0s are shifted in.

Figure v.17. (A) Shifting series data into shift register. (B) Shifting series data out of shift annals.

SRs are often used for parallel-to-series and serial-to-parallel conversions. A serial-to-parallel conversion is shown in Fig. 5.18A. The SR initially contains all binary 0s. So serial data is shifted in, and the output is taken in parallel from the FF outputs. For parallel-to-series conversion, a binary give-and-take is initially stored in the register. Then the word is shifted out as the clock pulses occur (see Fig. 5.18B).

Effigy 5.18. Shift registers used for (A) serial-to-parallel data conversion and (B) parallel-to-serial data conversion.

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Logic Emulation with Virtual Wires

Jonathan Babb , ... Anant Agarwal , in Readings in Hardware/Software Co-Design, 2002

B Shift Annals Architectures

We now compare three shift register architectures synthesizable to Xilinx 4000 FPGA'southward.

Full Shift Annals: The total shift register compages was originally proposed as a proof-of-concept virtual wires implementation [7]. This architecture consists of identical input and output shift loops (Fig. 17). In output mode, shift loops load emulated signal states at the beginning of each phase, and shift these states out serially onto a routed physical connection at the microcycle rate. For connections requiring multiple hops, a one-chip shift register is placed in each intermediate FPGA (Fig. 18), forming a shift register pipeline between source and destination. At the end of the pipeline, respective input fashion shift loops demultiplex and latch the emulated signals, and drive them into the emulated logic. Notation that the input shift loops must store their state so that all emulated logic inputs are available for subsequent evaluation. Output logic, however, can exist reused for multiple groups of emulation signals in different phases. To support per-phase routing, each inter-FPGA I/O pad is preceded past a multiplexer that selects the advisable shift loop output during its active phase. Pads are bidirectional with the pad driver enable signal asserted during phases in which that pad is an output. To minimize associated pad logic, the synthesizer groups inputs and outputs separately when possible.

Fig. 17. Full shift annals architecture.

Fig. eighteen. Intermediate hop architecture.

Gated Shift Register: To reduce the virtual wires consumption of core FPGA resources, the synthesizer can utilise architecture-specific FPGA features. In low-cost, low-pivot-count FPGA parts, many of the I/O pads are not continued to pins, and the synthesizer tin concatenate their registers to form virtual wires shift registers (Fig. 19). Due to pad configuration constraints, these shift registers cannot be parallel-loaded, and then they are not usable for output shift groups. Even so, the synthesizer tin place input shift groups and intermediate hop shift registers here. Since input shift groups must hold the emulated signal state after receiving it, and these I/O registers do not have clock enables, the synthesizer generates and distributes a gated μCLK. During the portions of the virtual wires cycle in which the emulated logic is being evaluated, this clock is frozen. In addition, the length of the input shift groups is adapted to dissever evenly into the number of μCLK's between evaluation periods so that the state in these registers tin can recirculate without change. In the 84-pin PLCC Xilinx 4005, this approach recovered 102 input and hop shift annals bits. Withal, clock gating and the slower timing of the I/O pad registers reduced the achievable μCLK rate.

Fig. 19. Gated shift registers using pad registers.

Addressable Shift Register: A further variation is to replace the output shift-grouping shift registers with tristate multiplexers available in the Xilinx compages (Fig. 20). The synthesizer creates an additional gear up of global control signals, labeled wheel enables, to enable each bit of the multiplexer during the appropriate microclock tick of each virtual wires phase. The synthesizer also replaces the input shift registers with sets of private register bits whose clock enables are controlled by the phase signal as before, only whose clocks are successive cycle enables. This architecture considerably reduces the cost of the virtual wires shift loops in terms of logic resources, but the additional control signals and the utilise of the tristate multiplexers add together routing overhead. This overhead is reduced somewhat past placing many of the boosted signals on global clock nets. Also, strategic utilize of the I/O pad registers for pipelining recovers speed. Finally, this architecture can support the more flexible virtual wires scheduling methods described in [32].

Fig. 20. Addressable shift loop architecture.

Comparisons: Tabular array I compares each compages in implementing the smallest benchmark excursion, Palindrome (see Section Five-A), on the 16-FPGA demonstration hardware presented in Section Five. Speed is measured in terms of the μCLK speed. We calculated overhead equally a percentage of consumed resources taken up by virtual wires. This virtual wire resources consumption is computed by subtracting the emulation logic resource consumption from total resource consumption. We measured emulation logic resource consumption by compiling unvirtualized partitions onto high-pivot-count FPGA'due south. CLB refers to the basic Xilinx combinational logic cake, which includes both combinational lookup tables and sequential registers. We list the programmable interconnect points (PIP's) equally reported by the Xilinx router. Note that the reported numbers are for hardware emulation, and exercise not include whatever additional speed and resource overheads that may be attributed to simulation dispatch.

TABLE I. ARCHITECTURAL COMPARISON

Resource	Design Logic	Full Logic (Virtual Overhead)
		Fig	Fig	Fig
Packed CLBs	54	79	80	65
(Total)		(32%)	(33%)	(17%)
Lookup Tables	115	165	167	131
(Combinational)		(30%)	(31%)	(12%)
Registers	74	141	102	115
(Sequential)		(48%)	(27%)	(36%)
Xilinx PIPs	1009	1729	1948	1612
(Routing)		(42%)	(48%)	(37%)
Average Resource Usage per FPGA
μCLK Speed		33MHz	24MHz	25MHz
Emulation Speed		1.2MHz	.89MHz	.93MHz

Maximum Clock Speed

The total shift register implementation is relatively fast, merely has significant overhead. The gated shift register architecture using the I/O pad registers is somewhat slower due to the reduced speed of these registers. This version does use fewer of the core registers, just routing overhead is higher because of the greater wiring distances covered between the pad registers and the core logic. Finally, the addressable scheme generally has lower logic and routing overhead while maintaining moderate speed. The results in the rest of this paper are based on the basic total shift register scheme, although we believe the addressable scheme to exist the best of the three schemes because it can back up more sophisticated scheduling algorithms as described in [32].

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Introduction to Digital Logic Blueprint

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

5.5.8 Digital Scan Path

The shift register is used to support excursion and organization testing. This arrangement forms a scan path [ 12]. Browse path testing is the main method to provide access for internal node controllability and observability of digital sequential logic circuits, where:

•

controllability is the power to control specific parts of a design to fix particular logic values at specific points.

•

observability is the ability to observe the response of a circuit to a particular excursion stimulus.

In scan path, the circuit is designed for 2 modes of performance:

•

normal operating mode, in which the circuit is running according to its required end-user part

•

browse test manner, in which logic values are serially clocked into circuit flip-bomb elements from an external indicate source, and the results are serially clocked out for external monitoring.

The incorporation of a scan path into a design requires additional inputs and outputs specifically used for the exam procedure. These inputs and outputs, and the browse test circuitry, are not used past the finish user.

Scan test inputs:

•

Scan data input (SDI) scans the data to clock serially into the circuit.

•

Scan enable (SE) enables the scan path mode.

Scan test output:

•

Scan data out (SDO) scans the data (results) that are serially clocked out of the scan path for external monitoring.

Using the basic circuit arrangement shown in Effigy v.77, the D-blazon flip-flops within the sequential logic circuit are put into a serial-in, series-out shift register every bit shown in Effigy five.78, showing SDI and SDO. The parallel outputs (Q0, Q1, Q2, and Q3) form inputs to the combinational logic inside the design.

Figure five.78. Browse test shift annals

A typical browse path test arrangement is shown in Figure 5.79, including the combinational logic block and D-blazon flip-flops. Each flip-bomb has a common clock and reset input. Between the flip-bomb D input and the combinational logic (the next country logic), a two-input multiplexer is inserted. The starting time data input to the multiplexer is the output from the adjacent country logic. The second information input comes from the Q output of a flip-bomb. This allows either of these signals to exist practical to the D input of the flip-flop using the select input on the multiplexer (connected to SE).

Figure 5.79. Scan path insertion using D-blazon flip-flops and multiplexers

In normal operating manner, the next state logic is continued to the flip-flop D input. In scan test mode, the Q output from a previous flip-flop is connected to the flip-flop D input. This isolates the flip-flop from the next state logic, and the flip-flops form a shift register of the class shown in Figure v.78. Test data tin can therefore be scanned in (using the SDI input), and test results can exist scanned out (using the SDO output). An example operation of this browse path follows:

1.

The circuit is put into scan test mode (by command of the SE). The exam data is serially scanned into the blueprint to prepare the flip-flop Q outputs to known values (i.east., to put the circuit into a known, initial country) by applying the test data to the SDI pin.

2.

The excursion is put back into its normal operating fashion and operated for a fix number of clock cycles.

three.

The circuit is once more put into browse test mode. The results of the test are stored on the Q outputs of the flip-flops and serially scanned out and monitored on the SDO pin.

iv.

The monitored values are compared with the expected values, and the excursion is then checked to see if information technology has passed (expected values received) or failed (the excursion output is not as expected) the test.

The system shown in Figure 5.79 uses a discrete multiplexer and D-type flip-flop to create the scan path. In many circuits, these functions are combined into a single scan D-type flip-bomb circuit element, as shown in Figure 5.80. This has the aforementioned logic functionality as a discrete flip-flop and multiplexer organization, but is optimized for size and speed of operation. It has two data inputs (D, normal data, and SD, scan data input) and a scan enable (SE) control input to select between normal and scan examination modes, in addition to the clock, reset (and/or ready) inputs and Q/Not-Q outputs.

Effigy 5.80. Browse D-blazon flip-flop

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Counters

Peter Wilson , in Design Recipes for FPGAs (2d Edition), 2016

24.five Shift Register

While a shift register is, strictly speaking, not a counter, it is useful to consider this in the context of other counters every bit it can be converted into a counter with very pocket-size changes. We volition consider this chemical element layer in this volume, in more than detail, merely consider a elementary case of a shift register that takes a single bit and stores in the least significant fleck of a register and shifts each bit up 1 bit on the occurrence of a clock edge. If we consider an n-bit register and show the status before and after a clock edge, then the functionality of the shift register becomes articulate, every bit shown in Figure 24.4.

Figure 24.4. Uncomplicated shift annals functionality: (a) Earlier the clock edge; (b) Subsequently the clock border.

A basic shift annals can be implemented in VHDL as shown here:

1   library ieee;

2   use ieee.std_logic_1164.all;

3

4   entity shift_register is

five   generic (

half-dozen     n : integer := 4;

7   port (

8     clk : in std_logic ;

9     rst : in std_logic ;

10     din : in std_logic;

11     q : out std_logic_vector (( northward −ane) downto 0)

12   );

thirteen   end entity;

14

fifteen   architecture uncomplicated of shift_register is

xvi   begin

17   process ( clk , rst )

18     variable shift_reg : std_logic_vector (( northward −one) downto 0);

nineteen   begin

xx     if rst = '0' and then

21     shift_reg := ( others => '0');

22     elsif rising_edge ( clk ) then

23     shift_reg := shift_reg ( northward −2 downto 0) & din;

24     cease if;

25     q <= shift_reg;

26   end procedure;

27   end architecture unproblematic;

The interesting parts of this model are very similar to the uncomplicated binary counter, only subtly dissimilar. As for the counter, we take defined an internal variable (shift_reg), but dissimilar the counter we practice not need to carry out arithmetic functions, then we do not need to define this as an unsigned variable. Instead, we can define straight every bit a std_logic_vector, the same as the output q.

Detect that nosotros have an asynchronous clock in this case. As nosotros have discussed previously in this book, at that place are techniques for completely synchronous sets or resets, and these can exist used if required.

The key difference between the counter and the shift register is in how we motion the bits around. In the counter nosotros employ arithmetic to add one to the internal counter variable (count). In this case, nosotros merely require shifting the register upward by one fleck, and to achieve this we merely assign the lowest (n − 1) bits of the internal register variable (shift_reg) to the upper (n − 1) $.25 and concatenate the input fleck (din), effectively setting the lowest bit of the register to the input signal (din). This can exist accomplished using the VHDL following:

1   shift_reg := shift_reg ( n −2 downto 0) & din;

The final stage of the model is similar to the basic counter in that we then assign the output signal to the value of the internal variable (shift_reg) using a standard indicate assignment. In the shift annals, nosotros do not need to cast the type as both the internal and signal variable types are std_logic_vector:

We can also implement the shift register in Verilog, with the list equally shown here:

i   module shift_register (

two   clk ,             // clock input

3   rst ,             // reset ( active low )

four   din ,             // Digital Input

v   shiftreg     // shift register

six    );

7

8   input clk;

9   input rst;

ten   input din;

11

12   output [vii:0] shiftreg ;

13

14   wire clk;

15   wire rst;

sixteen   wire din;

17

eighteen   reg [7:0] shiftreg ;

19

twenty   e'er @ (posedge clk)

21   brainstorm : count

22    if (rst == ane'b0) begin

23     shiftreg <= #one 4'b00000000;

24    stop

25    else begin

26     shiftreg <= #1 {din, shiftreg[7:1]};

27    finish

28   end

29

30   endmodule

In both cases (VHDL and Verilog) nosotros can exam the behavior of the shift register past applying a information sequence and observing the shift register variable in the model, and in the case of the Verilog we can also add a $monitor command to brandish the transitions equally they happen in the transcript of the simulator. The Verilog test bench code is given as:

ane

2   module shift_register_tb ();

3   // declare the signals

4   reg clk;

5   reg rst;

6   reg din;

7   wire [vii:0] shift_register_values;

eight

9   // Fix the initial variables and reset

10   initial brainstorm

eleven   $display ( " time ∖ t clk reset counter " );

12   $monitor ( " % grand ∖ t % b %b %b %h",

13    $time, clk, rst, din, shift_register_values);

14    clk = 1;   // initialize the clock to ane

15    rst = 1;   // fix the reset to 1 (non reset)

16    din = 0;      // Initialize the digital input

17    #5 rst = 0;   // reset = 0 : resets the counter

xviii    #10 rst = one; // reset back to one : counter can start

19    #iv din = 0; // exam data sequence starting at cycle time 16

20    #10 din = 1; // din = 1 test data sequence

21    #x din = 0; // din = 0 test data sequence

22    #ten din = 0; // din = 0 test data sequence

23    #10 din = one; // din = 1 test data sequence

24    #10 din = 1; // din = 1 test data sequence

25    #10 din = 0; // din = 0 test information sequence

26    #10 din = one; // din = 1 test data sequence

27    #10 din = 0; // din = 0 exam information sequence

28    #10 din = 1; // din = one test data sequence

29    #1000 $finish;   // Finish the simulation

xxx   end

31

32   // Clock generator

33   always brainstorm

34    #five clk = ˜clk; // Clock every 5 time slots

35   end

36

37   // Connect DUT to test bench

38   shift_register DUT (

39   clk,

40   rst,

41   din,

42   shift_register_values

43   );

44

45   endmodule

The resulting simulation of the shift register tin can be seen in Effigy 24.5.

Effigy 24.5. Simple shift annals simulation.

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Flip-flops and flip-bomb based circuits

John Crowe , Barrie Hayes-Gill , in Introduction to Digital Electronics, 1998

Sequence generator

If a binary pattern is fed into a shift annals information technology tin can so exist output serially to produce a known binary sequence. Moreover, if the output is also fed dorsum into the input (to class a SISO connected to itself) the same binary sequence can be generated indefinitely.

When a SISO shift register is connected to itself this is usually referred to as a re-entrant shift register, dynamic shift register, ring buffer or circulating memory. Variations on this type of excursion are used for data encryption, error checking and for holding information during digital signal processing.

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Simple Designs

Gina R. Smith , in FPGAs 101, 2010

Lines 23–28

Each chip is assigned the value of the data bit to its correct.

Pick 1 is okay for smaller shift registers, but it can exist fourth dimension consuming for larger numbers of bits. Option ii uses the reserved word downto to represent the individual shifts with fewer lines of code.

Lines 7–8. Shift Register Shortcut

Call back, in the signal assignment, the MSB number is written prior to downto with the LSB following. With that in mind, the point assignments for internal_shift_data_out in the shift_values procedure can be rewritten using downto, as shown in Listing 2-nine.

Listing ii-9

Simplified Shift Annals

1.   shift_values: Process (clk, reset)

2. Begin

3. If reset = '1' And so

iv.   shifted_data_out   &lt;= ((Others =&gt; '0'));

5. Elsif rising_edge (clk) Then

vi. -- this is the shortcut to creating a shift register

vii.   internal_shifted_data_out(0)   &lt;= shift_data;

8.   internal_shifted_data_out(5 downto 1) &lt;= internal_ shifted_data_out(4 downto 0);

9. Finish if;

10. Cease Process;

The downto bespeak consignment means that internal_shifted_data_out bit one is assigned the value of internal_shifted_data_out bit 0, internal_shifted_ data_out chip 2 is assigned the value of internal_shifted_data_out scrap 1 , and then on. The shift register signal consignment tin exist written using one betoken statement; notwithstanding, the operator for that assignment is not discussed in this book.

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Which Of The Following Is A Shift Register Counter,

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